URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 175

Rev	Log message	Author	Age	Path
138	Change buffering to save one clock per instruction.	simont	7738d 17h	/8051/tags/rel_12/rtl/verilog/
137	change to fit xrom.	simont	7738d 22h	/8051/tags/rel_12/rtl/verilog/
136	registering outputs.	simont	7738d 22h	/8051/tags/rel_12/rtl/verilog/
135	prepared start of receiving if ren is not active.	simont	7744d 21h	/8051/tags/rel_12/rtl/verilog/
134	fix bug in case execution of two data dependent instructions.	simont	7744d 21h	/8051/tags/rel_12/rtl/verilog/
133	fix bug in substraction.	simont	7745d 00h	/8051/tags/rel_12/rtl/verilog/
132	change branch instruction execution (reduse needed clock periods).	simont	7748d 15h	/8051/tags/rel_12/rtl/verilog/
128	chance idat_ir to 24 bit wide	simont	7757d 23h	/8051/tags/rel_12/rtl/verilog/
127	fix bug (cyc_o and stb_o)	simont	7757d 23h	/8051/tags/rel_12/rtl/verilog/
126	define OC8051_XILINX_RAMB added	simont	7757d 23h	/8051/tags/rel_12/rtl/verilog/