URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 186

Rev	Log message	Author	Age	Path
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7721d 09h	/8051/tags/rel_12/rtl/verilog/
144	chsnge comp.des to des1	simont	7721d 09h	/8051/tags/rel_12/rtl/verilog/
143	add wire sub_result, conect it to des_acc and des1.	simont	7721d 09h	/8051/tags/rel_12/rtl/verilog/
142	optimize state machine.	simont	7722d 10h	/8051/tags/rel_12/rtl/verilog/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7722d 12h	/8051/tags/rel_12/rtl/verilog/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7722d 12h	/8051/tags/rel_12/rtl/verilog/
139	add aditional alu destination to solve critical path.	simont	7723d 06h	/8051/tags/rel_12/rtl/verilog/
138	Change buffering to save one clock per instruction.	simont	7723d 06h	/8051/tags/rel_12/rtl/verilog/
137	change to fit xrom.	simont	7723d 11h	/8051/tags/rel_12/rtl/verilog/
136	registering outputs.	simont	7723d 11h	/8051/tags/rel_12/rtl/verilog/