URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 67

Rev	Log message	Author	Age	Path
23	mul & div use 4 clocks	simont	8023d 07h	/8051/tags/rel_12/rtl/verilog/
22	fix some bugs	simont	8023d 07h	/8051/tags/rel_12/rtl/verilog/
21	mul bug fixed	markom	8023d 12h	/8051/tags/rel_12/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	8023d 14h	/8051/tags/rel_12/rtl/verilog/
19	combinatorial loop removed	simont	8024d 07h	/8051/tags/rel_12/rtl/verilog/
17	fix some bugs	simont	8027d 12h	/8051/tags/rel_12/rtl/verilog/
16	inputs ram and op2 removed	simont	8027d 12h	/8051/tags/rel_12/rtl/verilog/
15	commbinatorial loop removed	simont	8027d 12h	/8051/tags/rel_12/rtl/verilog/
13	some bug fix	simont	8028d 10h	/8051/tags/rel_12/rtl/verilog/
12	des1_r in alu port list	simont	8028d 10h	/8051/tags/rel_12/rtl/verilog/