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URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [tags/] [rel_2/] - Rev 113

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Rev Log message Author Age Path
93 OC8051_XILINX_RAM added simont 7777d 21h /8051/tags/rel_2/
92 initial inport simont 7777d 21h /8051/tags/rel_2/
91 *** empty log message *** simont 7777d 21h /8051/tags/rel_2/
90 change module name. simont 7782d 15h /8051/tags/rel_2/
89 Replaced oc8051_ram by generic_dpram. rherveille 7843d 18h /8051/tags/rel_2/
88 fix bugs simont 7848d 19h /8051/tags/rel_2/
87 add include oc8051_defines.v simont 7848d 19h /8051/tags/rel_2/
86 initial input simont 7848d 19h /8051/tags/rel_2/
85 prepare bugs simont 7848d 19h /8051/tags/rel_2/
84 remove wb_bus_mon simont 7856d 18h /8051/tags/rel_2/

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