URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 135

Rev	Log message	Author	Age	Path
115	change uart to meet timing.	simont	7802d 03h	/8051/tags/rel_2/
114	remove t2mod register	simont	7805d 06h	/8051/tags/rel_2/
113	signal prsc_ow added.	simont	7805d 06h	/8051/tags/rel_2/
112	change timers to meet timing specifications (add divider with 12)	simont	7805d 06h	/8051/tags/rel_2/
111	Remove instruction cache and wb_interface	simont	7805d 21h	/8051/tags/rel_2/
110	change adr_i and adr_o length.	simont	7805d 21h	/8051/tags/rel_2/
109	add `include "oc8051_defines.v"	simont	7805d 21h	/8051/tags/rel_2/
108	fix some bugs, use oc8051_cache_ram.	simont	7805d 21h	/8051/tags/rel_2/
107	Include instruction cache.	simont	7805d 21h	/8051/tags/rel_2/
106	generic_dpram used	simont	7807d 00h	/8051/tags/rel_2/