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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] - Rev 186

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Rev Log message Author Age Path
97 initial inport simont 7745d 17h /8051/tags/rel_2/bench/
96 initial import simont 7745d 17h /8051/tags/rel_2/bench/
84 remove wb_bus_mon simont 7824d 14h /8051/tags/rel_2/bench/
74 add module oc8051_wb_iinterface simont 7901d 12h /8051/tags/rel_2/bench/
68 add instruction cache and DELAY parameters for external ram, rom simont 7905d 15h /8051/tags/rel_2/bench/
59 add external rom simont 7912d 10h /8051/tags/rel_2/bench/
46 prepared header simont 7929d 11h /8051/tags/rel_2/bench/
37 added signals ack, stb and cyc simont 7956d 14h /8051/tags/rel_2/bench/
4 Code repaired to satisfy the linter; testbech fails markom 7976d 17h /8051/tags/rel_2/bench/
2 Initial CVS import simont 7992d 15h /8051/tags/rel_2/bench/

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