URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 132

Rev	Log message	Author	Age	Path
105	generic_dpram used	simont	7747d 21h	/8051/trunk/rtl/verilog/
104	use generic_dpram	simont	7747d 21h	/8051/trunk/rtl/verilog/
102	raname signals.	simont	7747d 22h	/8051/trunk/rtl/verilog/
95	updating...	simont	7748d 01h	/8051/trunk/rtl/verilog/
94	fix bug.	simont	7748d 02h	/8051/trunk/rtl/verilog/
93	OC8051_XILINX_RAM added	simont	7748d 02h	/8051/trunk/rtl/verilog/
92	initial inport	simont	7748d 02h	/8051/trunk/rtl/verilog/
90	change module name.	simont	7752d 19h	/8051/trunk/rtl/verilog/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7813d 23h	/8051/trunk/rtl/verilog/
88	fix bugs	simont	7818d 23h	/8051/trunk/rtl/verilog/