URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 148

Rev	Log message	Author	Age	Path
122	deifne OC8051_ROM added	simont	7749d 02h	/8051/trunk/rtl/verilog/
121	Change pc add value from 23'h to 16'h	simont	7749d 02h	/8051/trunk/rtl/verilog/
120	defines for pherypherals added	simont	7749d 23h	/8051/trunk/rtl/verilog/
119	remove signal sbuf_txd [12:11]	simont	7750d 03h	/8051/trunk/rtl/verilog/
118	change wr_sft to 2 bit wire.	simont	7750d 20h	/8051/trunk/rtl/verilog/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7750d 20h	/8051/trunk/rtl/verilog/
116	change sfr's interface.	simont	7752d 21h	/8051/trunk/rtl/verilog/
115	change uart to meet timing.	simont	7752d 23h	/8051/trunk/rtl/verilog/
114	remove t2mod register	simont	7756d 02h	/8051/trunk/rtl/verilog/
113	signal prsc_ow added.	simont	7756d 02h	/8051/trunk/rtl/verilog/