URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 179

Rev	Log message	Author	Age	Path
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7737d 08h	/8051/trunk/rtl/verilog/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7737d 08h	/8051/trunk/rtl/verilog/
139	add aditional alu destination to solve critical path.	simont	7738d 02h	/8051/trunk/rtl/verilog/
138	Change buffering to save one clock per instruction.	simont	7738d 02h	/8051/trunk/rtl/verilog/
137	change to fit xrom.	simont	7738d 07h	/8051/trunk/rtl/verilog/
136	registering outputs.	simont	7738d 07h	/8051/trunk/rtl/verilog/
135	prepared start of receiving if ren is not active.	simont	7744d 06h	/8051/trunk/rtl/verilog/
134	fix bug in case execution of two data dependent instructions.	simont	7744d 06h	/8051/trunk/rtl/verilog/
133	fix bug in substraction.	simont	7744d 09h	/8051/trunk/rtl/verilog/
132	change branch instruction execution (reduse needed clock periods).	simont	7748d 00h	/8051/trunk/rtl/verilog/