URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 185

Rev	Log message	Author	Age	Path
143	add wire sub_result, conect it to des_acc and des1.	simont	7713d 01h	/8051/trunk/rtl/verilog/
142	optimize state machine.	simont	7714d 02h	/8051/trunk/rtl/verilog/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7714d 03h	/8051/trunk/rtl/verilog/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7714d 04h	/8051/trunk/rtl/verilog/
139	add aditional alu destination to solve critical path.	simont	7714d 21h	/8051/trunk/rtl/verilog/
138	Change buffering to save one clock per instruction.	simont	7714d 21h	/8051/trunk/rtl/verilog/
137	change to fit xrom.	simont	7715d 03h	/8051/trunk/rtl/verilog/
136	registering outputs.	simont	7715d 03h	/8051/trunk/rtl/verilog/
135	prepared start of receiving if ren is not active.	simont	7721d 02h	/8051/trunk/rtl/verilog/
134	fix bug in case execution of two data dependent instructions.	simont	7721d 02h	/8051/trunk/rtl/verilog/