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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 194

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Rev Log message Author Age Path
84 Added interrupt support. sybreon 6050d 05h /aemb/branches/DEV_SYBREON/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6050d 05h /aemb/branches/DEV_SYBREON/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6052d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6052d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6053d 14h /aemb/branches/DEV_SYBREON/rtl/verilog/
78 initial import sybreon 6055d 08h /aemb/branches/DEV_SYBREON/rtl/verilog/
76 initial sybreon 6058d 14h /aemb/branches/DEV_SYBREON/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6065d 16h /aemb/branches/DEV_SYBREON/rtl/verilog/
72 Minor code cleanup. sybreon 6065d 16h /aemb/branches/DEV_SYBREON/rtl/verilog/
71 Old version deprecated. sybreon 6072d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/

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