URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 55

Rev	Log message	Author	Age	Path
23	Fixed minor simulation bug.	sybreon	6346d 16h	/aemb/branches/DEV_SYBREON/rtl/verilog/
22	Added support for 8-bit and 16-bit data types.	sybreon	6346d 16h	/aemb/branches/DEV_SYBREON/rtl/verilog/
19	Added initial unified memory core.	sybreon	6359d 02h	/aemb/branches/DEV_SYBREON/rtl/verilog/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6359d 18h	/aemb/branches/DEV_SYBREON/rtl/verilog/
17	Cosmetic changes	sybreon	6360d 22h	/aemb/branches/DEV_SYBREON/rtl/verilog/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6361d 10h	/aemb/branches/DEV_SYBREON/rtl/verilog/
14	Added initial interrupt/exception support.	sybreon	6368d 01h	/aemb/branches/DEV_SYBREON/rtl/verilog/
11	Removed unused signals	sybreon	6368d 08h	/aemb/branches/DEV_SYBREON/rtl/verilog/
10	Fixed minor bugs	sybreon	6368d 09h	/aemb/branches/DEV_SYBREON/rtl/verilog/
9	Extended testbench code	sybreon	6368d 09h	/aemb/branches/DEV_SYBREON/rtl/verilog/