URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 85

Rev	Log message	Author	Age	Path
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6124d 17h	/aemb/branches/DEV_SYBREON/rtl/verilog/
50	Parameterised optional components.	sybreon	6124d 20h	/aemb/branches/DEV_SYBREON/rtl/verilog/
48	Fixed spurious interrupt latching during long bus cycles (spotted by J Lee).	sybreon	6129d 05h	/aemb/branches/DEV_SYBREON/rtl/verilog/
45	Minor code cleanup.	sybreon	6130d 02h	/aemb/branches/DEV_SYBREON/rtl/verilog/
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6130d 15h	/aemb/branches/DEV_SYBREON/rtl/verilog/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6131d 07h	/aemb/branches/DEV_SYBREON/rtl/verilog/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6141d 15h	/aemb/branches/DEV_SYBREON/rtl/verilog/
38	Added interrupt support.	sybreon	6286d 16h	/aemb/branches/DEV_SYBREON/rtl/verilog/
36	Removed asynchronous reset signal.	sybreon	6300d 02h	/aemb/branches/DEV_SYBREON/rtl/verilog/
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6300d 22h	/aemb/branches/DEV_SYBREON/rtl/verilog/