URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 85

Rev	Log message	Author	Age	Path
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6153d 20h	/aemb/trunk/rtl/verilog/
50	Parameterised optional components.	sybreon	6154d 00h	/aemb/trunk/rtl/verilog/
48	Fixed spurious interrupt latching during long bus cycles (spotted by J Lee).	sybreon	6158d 09h	/aemb/trunk/rtl/verilog/
45	Minor code cleanup.	sybreon	6159d 06h	/aemb/trunk/rtl/verilog/
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6159d 19h	/aemb/trunk/rtl/verilog/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6160d 11h	/aemb/trunk/rtl/verilog/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6170d 19h	/aemb/trunk/rtl/verilog/
38	Added interrupt support.	sybreon	6315d 19h	/aemb/trunk/rtl/verilog/
36	Removed asynchronous reset signal.	sybreon	6329d 05h	/aemb/trunk/rtl/verilog/
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6330d 02h	/aemb/trunk/rtl/verilog/