URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] - Rev 209

Rev	Log message	Author	Age	Path
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6068d 06h	/aemb/trunk/sim/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6069d 04h	/aemb/trunk/sim/
53	Added GET/PUT support through a FSL bus.	sybreon	6073d 07h	/aemb/trunk/sim/
52	Added log output to iverilog.log	sybreon	6073d 07h	/aemb/trunk/sim/
50	Parameterised optional components.	sybreon	6074d 13h	/aemb/trunk/sim/
49	Added random seed for simulation.	sybreon	6077d 17h	/aemb/trunk/sim/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6080d 09h	/aemb/trunk/sim/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6081d 00h	/aemb/trunk/sim/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6091d 09h	/aemb/trunk/sim/
38	Added interrupt support.	sybreon	6236d 09h	/aemb/trunk/sim/