URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 200

Rev	Log message	Author	Age	Path
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6127d 11h	/aemb/trunk/sim/verilog/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6137d 19h	/aemb/trunk/sim/verilog/
38	Added interrupt support.	sybreon	6282d 20h	/aemb/trunk/sim/verilog/
31	Removed byte acrobatics.	sybreon	6312d 23h	/aemb/trunk/sim/verilog/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6315d 23h	/aemb/trunk/sim/verilog/
22	Added support for 8-bit and 16-bit data types.	sybreon	6317d 16h	/aemb/trunk/sim/verilog/
19	Added initial unified memory core.	sybreon	6330d 02h	/aemb/trunk/sim/verilog/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6330d 18h	/aemb/trunk/sim/verilog/