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[/] [amber/] - Rev 41

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21 Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start. csantifort 4864d 11h /amber/
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.		 csantifort 4885d 12h /amber/
19 Create a configuration log file as part of the synthesis flow. This file is a useful reference to
tell the different bitfiles apart.		 csantifort 4885d 12h /amber/
18 Added list of source files and diagram for Amber25 core. csantifort 4888d 11h /amber/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions		 csantifort 4889d 10h /amber/
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.		 csantifort 4892d 00h /amber/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 4892d 00h /amber/
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.		 csantifort 4893d 12h /amber/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.		 csantifort 4893d 12h /amber/
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.		 csantifort 4893d 12h /amber/

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