URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] - Rev 61

Rev	Log message	Author	Age	Path
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	4752d 06h	/amber/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	4756d 23h	/amber/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	4758d 00h	/amber/
38	support 128-bit wishbone now used for a25 core	csantifort	4759d 00h	/amber/
37	128-bit wide boot memory module	csantifort	4759d 22h	/amber/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4759d 23h	/amber/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4761d 06h	/amber/
34	Tweaked strcpy function to speed it up slightly	csantifort	4762d 03h	/amber/
33	Fixed bug in div assembly function. Handles negative numbers correctly. Fixed bug in printf function, negative numbers now print correctly.	csantifort	4762d 23h	/amber/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	4763d 23h	/amber/