URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 61

Rev	Log message	Author	Age	Path
32	abort_tx added. Bit destuff fixed.	mohor	7854d 23h	/can/tags/rel_12/rtl/verilog/
31	Wishbone interface added.	mohor	7856d 12h	/can/tags/rel_12/rtl/verilog/
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7856d 21h	/can/tags/rel_12/rtl/verilog/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7857d 19h	/can/tags/rel_12/rtl/verilog/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7858d 11h	/can/tags/rel_12/rtl/verilog/
27	This file is not used.	mohor	7862d 20h	/can/tags/rel_12/rtl/verilog/
26	Backup.	mohor	7862d 20h	/can/tags/rel_12/rtl/verilog/
25	* empty log message *	mohor	7862d 23h	/can/tags/rel_12/rtl/verilog/
24	backup.	mohor	7867d 12h	/can/tags/rel_12/rtl/verilog/
23	Fifo corrected to be synthesizable.	mohor	7880d 19h	/can/tags/rel_12/rtl/verilog/