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[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 81

Rev	Log message	Author	Age	Path
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7798d 05h	/can/tags/rel_12/rtl/verilog/
56	Doubled declarations removed.	mohor	7799d 04h	/can/tags/rel_12/rtl/verilog/
55	wire declaration added.	mohor	7799d 04h	/can/tags/rel_12/rtl/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7804d 06h	/can/tags/rel_12/rtl/verilog/
51	Xilinx RAM added.	mohor	7804d 06h	/can/tags/rel_12/rtl/verilog/
50	Top level signal names changed.	mohor	7804d 06h	/can/tags/rel_12/rtl/verilog/
48	Actel APA ram supported.	mohor	7807d 22h	/can/tags/rel_12/rtl/verilog/
47	Data is latched on read.	mohor	7807d 22h	/can/tags/rel_12/rtl/verilog/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7817d 21h	/can/tags/rel_12/rtl/verilog/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7817d 22h	/can/tags/rel_12/rtl/verilog/