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Rev Log message Author Age Path
58 timescale.v is used for simulation only. mohor 7795d 13h /can/tags/rel_20/
57 Mux used for clkout to avoid "gated clocks warning". mohor 7795d 13h /can/tags/rel_20/
56 Doubled declarations removed. mohor 7796d 12h /can/tags/rel_20/
55 wire declaration added. mohor 7796d 12h /can/tags/rel_20/
53 CAN pins located. mohor 7801d 14h /can/tags/rel_20/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7801d 14h /can/tags/rel_20/
51 Xilinx RAM added. mohor 7801d 14h /can/tags/rel_20/
50 Top level signal names changed. mohor 7801d 14h /can/tags/rel_20/
49 Actel APA ram changed. Now synchronous read is used. mohor 7805d 06h /can/tags/rel_20/
48 Actel APA ram supported. mohor 7805d 06h /can/tags/rel_20/

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