URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] - Rev 161

Rev	Log message	Author	Age	Path
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7700d 10h	/can/tags/rel_22/rtl/verilog/
110	Fixed according to the linter.	mohor	7700d 10h	/can/tags/rel_22/rtl/verilog/
109	Fixed according to the linter.	mohor	7700d 11h	/can/tags/rel_22/rtl/verilog/
108	Fixed according to the linter.	mohor	7700d 12h	/can/tags/rel_22/rtl/verilog/
107	Fixed according to the linter.	mohor	7700d 12h	/can/tags/rel_22/rtl/verilog/
106	Unused signal removed.	mohor	7706d 10h	/can/tags/rel_22/rtl/verilog/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7707d 00h	/can/tags/rel_22/rtl/verilog/
102	Little fixes (to fix warnings).	mohor	7709d 14h	/can/tags/rel_22/rtl/verilog/
100	Synchronization changed.	mohor	7713d 16h	/can/tags/rel_22/rtl/verilog/
99	PCI_BIST replaced with CAN_BIST.	mohor	7713d 16h	/can/tags/rel_22/rtl/verilog/