URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] - Rev 70

Rev	Log message	Author	Age	Path
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7817d 20h	/can/tags/rel_22/rtl/verilog/
41	Incomplete sensitivity list fixed.	mohor	7818d 04h	/can/tags/rel_22/rtl/verilog/
40	Typo fixed.	mohor	7818d 04h	/can/tags/rel_22/rtl/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7818d 05h	/can/tags/rel_22/rtl/verilog/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7819d 19h	/can/tags/rel_22/rtl/verilog/
35	Several registers added. Not finished, yet.	mohor	7822d 23h	/can/tags/rel_22/rtl/verilog/
33	abort_tx added.	mohor	7825d 05h	/can/tags/rel_22/rtl/verilog/
32	abort_tx added. Bit destuff fixed.	mohor	7825d 05h	/can/tags/rel_22/rtl/verilog/
31	Wishbone interface added.	mohor	7826d 18h	/can/tags/rel_22/rtl/verilog/
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7827d 03h	/can/tags/rel_22/rtl/verilog/