URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 89

Rev	Log message	Author	Age	Path
61	Lapsus fixed.	simons	7679d 21h	/dbg_interface/tags/asyst_2/
59	Reset value for riscsel register set to 1.	simons	7679d 21h	/dbg_interface/tags/asyst_2/
57	Multiple cpu support added.	simons	7679d 23h	/dbg_interface/tags/asyst_2/
56	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7946d 19h	/dbg_interface/tags/asyst_2/
55	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7946d 19h	/dbg_interface/tags/asyst_2/
53	Trst active high. Inverted on higher layer.	mohor	7946d 21h	/dbg_interface/tags/asyst_2/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7946d 21h	/dbg_interface/tags/asyst_2/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7974d 08h	/dbg_interface/tags/asyst_2/
50	Revision 1.5 of the document ready. WISHBONE Scan Chain changed.	mohor	7974d 09h	/dbg_interface/tags/asyst_2/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8129d 20h	/dbg_interface/tags/asyst_2/