URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 99

Rev	Log message	Author	Age	Path
75	Simulation files.	mohor	7561d 05h	/dbg_interface/tags/asyst_2/
74	Removed.	mohor	7561d 05h	/dbg_interface/tags/asyst_2/
73	CRC logic changed.	mohor	7561d 06h	/dbg_interface/tags/asyst_2/
71	Mbist support added.	simons	7563d 12h	/dbg_interface/tags/asyst_2/
70	A pdf copy of existing doc document.	simons	7570d 14h	/dbg_interface/tags/asyst_2/
69	WBCNTL added, multiple CPU support described.	simons	7591d 03h	/dbg_interface/tags/asyst_2/
67	Lower two address lines must be always zero.	simons	7596d 08h	/dbg_interface/tags/asyst_2/
65	WB_CNTL register added, some syncronization fixes.	simons	7597d 07h	/dbg_interface/tags/asyst_2/
63	Three more chains added for cpu debug access.	simons	7617d 08h	/dbg_interface/tags/asyst_2/
61	Lapsus fixed.	simons	7645d 08h	/dbg_interface/tags/asyst_2/