URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 104

Rev	Log message	Author	Age	Path
73	CRC logic changed.	mohor	7547d 20h	/dbg_interface/tags/asyst_2/rtl/
71	Mbist support added.	simons	7550d 03h	/dbg_interface/tags/asyst_2/rtl/
67	Lower two address lines must be always zero.	simons	7582d 23h	/dbg_interface/tags/asyst_2/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7583d 22h	/dbg_interface/tags/asyst_2/rtl/
63	Three more chains added for cpu debug access.	simons	7603d 23h	/dbg_interface/tags/asyst_2/rtl/
61	Lapsus fixed.	simons	7631d 23h	/dbg_interface/tags/asyst_2/rtl/
59	Reset value for riscsel register set to 1.	simons	7631d 23h	/dbg_interface/tags/asyst_2/rtl/
57	Multiple cpu support added.	simons	7632d 00h	/dbg_interface/tags/asyst_2/rtl/
53	Trst active high. Inverted on higher layer.	mohor	7898d 22h	/dbg_interface/tags/asyst_2/rtl/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7898d 22h	/dbg_interface/tags/asyst_2/rtl/