URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 117

Rev	Log message	Author	Age	Path
82	New directory structure. New version of the debug interface.	mohor	7486d 22h	/dbg_interface/tags/asyst_2/rtl/
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7486d 22h	/dbg_interface/tags/asyst_2/rtl/
77	MBIST chain connection fixed.	mohor	7547d 19h	/dbg_interface/tags/asyst_2/rtl/
73	CRC logic changed.	mohor	7547d 21h	/dbg_interface/tags/asyst_2/rtl/
71	Mbist support added.	simons	7550d 04h	/dbg_interface/tags/asyst_2/rtl/
67	Lower two address lines must be always zero.	simons	7582d 23h	/dbg_interface/tags/asyst_2/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7583d 23h	/dbg_interface/tags/asyst_2/rtl/
63	Three more chains added for cpu debug access.	simons	7604d 00h	/dbg_interface/tags/asyst_2/rtl/
61	Lapsus fixed.	simons	7631d 23h	/dbg_interface/tags/asyst_2/rtl/
59	Reset value for riscsel register set to 1.	simons	7632d 00h	/dbg_interface/tags/asyst_2/rtl/