URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_3/] - Rev 99

Rev	Log message	Author	Age	Path
75	Simulation files.	mohor	7603d 04h	/dbg_interface/tags/asyst_3/
74	Removed.	mohor	7603d 04h	/dbg_interface/tags/asyst_3/
73	CRC logic changed.	mohor	7603d 04h	/dbg_interface/tags/asyst_3/
71	Mbist support added.	simons	7605d 11h	/dbg_interface/tags/asyst_3/
70	A pdf copy of existing doc document.	simons	7612d 13h	/dbg_interface/tags/asyst_3/
69	WBCNTL added, multiple CPU support described.	simons	7633d 02h	/dbg_interface/tags/asyst_3/
67	Lower two address lines must be always zero.	simons	7638d 07h	/dbg_interface/tags/asyst_3/
65	WB_CNTL register added, some syncronization fixes.	simons	7639d 06h	/dbg_interface/tags/asyst_3/
63	Three more chains added for cpu debug access.	simons	7659d 07h	/dbg_interface/tags/asyst_3/
61	Lapsus fixed.	simons	7687d 07h	/dbg_interface/tags/asyst_3/