URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] - Rev 51

Rev	Log message	Author	Age	Path
25	trst signal is synchronized to wb_clk_i.	mohor	8331d 07h	/dbg_interface/tags/old_debug/rtl/
23	Trace disabled by default.	mohor	8338d 11h	/dbg_interface/tags/old_debug/rtl/
22	Register length fixed.	mohor	8338d 11h	/dbg_interface/tags/old_debug/rtl/
21	CRC is returned when chain selection data is transmitted.	mohor	8339d 07h	/dbg_interface/tags/old_debug/rtl/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8340d 10h	/dbg_interface/tags/old_debug/rtl/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8352d 11h	/dbg_interface/tags/old_debug/rtl/
18	Reset signals are not combined any more.	mohor	8354d 20h	/dbg_interface/tags/old_debug/rtl/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8378d 09h	/dbg_interface/tags/old_debug/rtl/
15	bs_chain_o added.	mohor	8380d 10h	/dbg_interface/tags/old_debug/rtl/
13	Signal names changed to lowercase.	mohor	8381d 11h	/dbg_interface/tags/old_debug/rtl/