URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] - Rev 57

Rev	Log message	Author	Age	Path
28	TDO and TDO Enable signal are separated into two signals.	mohor	8239d 16h	/dbg_interface/tags/old_debug/rtl/verilog/
27	Warnings from synthesys tools fixed.	mohor	8253d 17h	/dbg_interface/tags/old_debug/rtl/verilog/
26	Warnings from synthesys tools fixed.	mohor	8253d 17h	/dbg_interface/tags/old_debug/rtl/verilog/
25	trst signal is synchronized to wb_clk_i.	mohor	8254d 13h	/dbg_interface/tags/old_debug/rtl/verilog/
23	Trace disabled by default.	mohor	8261d 17h	/dbg_interface/tags/old_debug/rtl/verilog/
22	Register length fixed.	mohor	8261d 17h	/dbg_interface/tags/old_debug/rtl/verilog/
21	CRC is returned when chain selection data is transmitted.	mohor	8262d 13h	/dbg_interface/tags/old_debug/rtl/verilog/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8263d 16h	/dbg_interface/tags/old_debug/rtl/verilog/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8275d 17h	/dbg_interface/tags/old_debug/rtl/verilog/
18	Reset signals are not combined any more.	mohor	8278d 02h	/dbg_interface/tags/old_debug/rtl/verilog/