URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] - Rev 59

Rev	Log message	Author	Age	Path
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8209d 13h	/dbg_interface/tags/old_debug/rtl/verilog/
28	TDO and TDO Enable signal are separated into two signals.	mohor	8245d 09h	/dbg_interface/tags/old_debug/rtl/verilog/
27	Warnings from synthesys tools fixed.	mohor	8259d 11h	/dbg_interface/tags/old_debug/rtl/verilog/
26	Warnings from synthesys tools fixed.	mohor	8259d 11h	/dbg_interface/tags/old_debug/rtl/verilog/
25	trst signal is synchronized to wb_clk_i.	mohor	8260d 07h	/dbg_interface/tags/old_debug/rtl/verilog/
23	Trace disabled by default.	mohor	8267d 11h	/dbg_interface/tags/old_debug/rtl/verilog/
22	Register length fixed.	mohor	8267d 11h	/dbg_interface/tags/old_debug/rtl/verilog/
21	CRC is returned when chain selection data is transmitted.	mohor	8268d 07h	/dbg_interface/tags/old_debug/rtl/verilog/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8269d 10h	/dbg_interface/tags/old_debug/rtl/verilog/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8281d 10h	/dbg_interface/tags/old_debug/rtl/verilog/