URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 45

Rev	Log message	Author	Age	Path
21	CRC is returned when chain selection data is transmitted.	mohor	8250d 05h	/dbg_interface/tags/rel_1/rtl/verilog/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8251d 08h	/dbg_interface/tags/rel_1/rtl/verilog/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8263d 09h	/dbg_interface/tags/rel_1/rtl/verilog/
18	Reset signals are not combined any more.	mohor	8265d 18h	/dbg_interface/tags/rel_1/rtl/verilog/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8289d 07h	/dbg_interface/tags/rel_1/rtl/verilog/
15	bs_chain_o added.	mohor	8291d 08h	/dbg_interface/tags/rel_1/rtl/verilog/
13	Signal names changed to lowercase.	mohor	8292d 09h	/dbg_interface/tags/rel_1/rtl/verilog/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8293d 09h	/dbg_interface/tags/rel_1/rtl/verilog/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8314d 05h	/dbg_interface/tags/rel_1/rtl/verilog/
9	Working version. Few bugs fixed, comments added.	mohor	8318d 09h	/dbg_interface/tags/rel_1/rtl/verilog/