URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] - Rev 100

Rev	Log message	Author	Age	Path
77	MBIST chain connection fixed.	mohor	7572d 13h	/dbg_interface/tags/rel_15/
75	Simulation files.	mohor	7572d 15h	/dbg_interface/tags/rel_15/
74	Removed.	mohor	7572d 15h	/dbg_interface/tags/rel_15/
73	CRC logic changed.	mohor	7572d 15h	/dbg_interface/tags/rel_15/
71	Mbist support added.	simons	7574d 21h	/dbg_interface/tags/rel_15/
70	A pdf copy of existing doc document.	simons	7581d 23h	/dbg_interface/tags/rel_15/
69	WBCNTL added, multiple CPU support described.	simons	7602d 13h	/dbg_interface/tags/rel_15/
67	Lower two address lines must be always zero.	simons	7607d 17h	/dbg_interface/tags/rel_15/
65	WB_CNTL register added, some syncronization fixes.	simons	7608d 17h	/dbg_interface/tags/rel_15/
63	Three more chains added for cpu debug access.	simons	7628d 17h	/dbg_interface/tags/rel_15/