URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] - Rev 88

Rev	Log message	Author	Age	Path
59	Reset value for riscsel register set to 1.	simons	7713d 03h	/dbg_interface/tags/rel_15/
57	Multiple cpu support added.	simons	7713d 05h	/dbg_interface/tags/rel_15/
56	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7980d 01h	/dbg_interface/tags/rel_15/
55	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7980d 01h	/dbg_interface/tags/rel_15/
53	Trst active high. Inverted on higher layer.	mohor	7980d 03h	/dbg_interface/tags/rel_15/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7980d 03h	/dbg_interface/tags/rel_15/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	8007d 14h	/dbg_interface/tags/rel_15/
50	Revision 1.5 of the document ready. WISHBONE Scan Chain changed.	mohor	8007d 15h	/dbg_interface/tags/rel_15/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8163d 02h	/dbg_interface/tags/rel_15/
46	Asynchronous reset used instead of synchronous.	mohor	8171d 09h	/dbg_interface/tags/rel_15/