URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] - Rev 91

Rev	Log message	Author	Age	Path
65	WB_CNTL register added, some syncronization fixes.	simons	7628d 18h	/dbg_interface/tags/rel_15/
63	Three more chains added for cpu debug access.	simons	7648d 19h	/dbg_interface/tags/rel_15/
61	Lapsus fixed.	simons	7676d 19h	/dbg_interface/tags/rel_15/
59	Reset value for riscsel register set to 1.	simons	7676d 19h	/dbg_interface/tags/rel_15/
57	Multiple cpu support added.	simons	7676d 20h	/dbg_interface/tags/rel_15/
56	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7943d 17h	/dbg_interface/tags/rel_15/
55	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7943d 17h	/dbg_interface/tags/rel_15/
53	Trst active high. Inverted on higher layer.	mohor	7943d 18h	/dbg_interface/tags/rel_15/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7943d 18h	/dbg_interface/tags/rel_15/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7971d 06h	/dbg_interface/tags/rel_15/