URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [bench/] [verilog/] - Rev 158

Rev	Log message	Author	Age	Path
36	Structure changed. Hooks for jtag chain added.	mohor	8156d 20h	/dbg_interface/tags/rel_15/bench/verilog/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8297d 00h	/dbg_interface/tags/rel_15/bench/verilog/
15	bs_chain_o added.	mohor	8299d 01h	/dbg_interface/tags/rel_15/bench/verilog/
13	Signal names changed to lowercase.	mohor	8300d 02h	/dbg_interface/tags/rel_15/bench/verilog/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8301d 02h	/dbg_interface/tags/rel_15/bench/verilog/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8321d 22h	/dbg_interface/tags/rel_15/bench/verilog/
9	Working version. Few bugs fixed, comments added.	mohor	8326d 02h	/dbg_interface/tags/rel_15/bench/verilog/
6	Minor changes for simulation.	mohor	8327d 00h	/dbg_interface/tags/rel_15/bench/verilog/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8327d 22h	/dbg_interface/tags/rel_15/bench/verilog/
2	Initial official release.	mohor	8332d 22h	/dbg_interface/tags/rel_15/bench/verilog/