URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 106

Rev	Log message	Author	Age	Path
77	MBIST chain connection fixed.	mohor	7566d 05h	/dbg_interface/tags/rel_15/rtl/
73	CRC logic changed.	mohor	7566d 07h	/dbg_interface/tags/rel_15/rtl/
71	Mbist support added.	simons	7568d 14h	/dbg_interface/tags/rel_15/rtl/
67	Lower two address lines must be always zero.	simons	7601d 10h	/dbg_interface/tags/rel_15/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7602d 09h	/dbg_interface/tags/rel_15/rtl/
63	Three more chains added for cpu debug access.	simons	7622d 10h	/dbg_interface/tags/rel_15/rtl/
61	Lapsus fixed.	simons	7650d 09h	/dbg_interface/tags/rel_15/rtl/
59	Reset value for riscsel register set to 1.	simons	7650d 10h	/dbg_interface/tags/rel_15/rtl/
57	Multiple cpu support added.	simons	7650d 11h	/dbg_interface/tags/rel_15/rtl/
53	Trst active high. Inverted on higher layer.	mohor	7917d 09h	/dbg_interface/tags/rel_15/rtl/