URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 95

Rev	Log message	Author	Age	Path
59	Reset value for riscsel register set to 1.	simons	7638d 22h	/dbg_interface/tags/rel_15/rtl/
57	Multiple cpu support added.	simons	7638d 23h	/dbg_interface/tags/rel_15/rtl/
53	Trst active high. Inverted on higher layer.	mohor	7905d 21h	/dbg_interface/tags/rel_15/rtl/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7905d 21h	/dbg_interface/tags/rel_15/rtl/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7933d 09h	/dbg_interface/tags/rel_15/rtl/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8088d 20h	/dbg_interface/tags/rel_15/rtl/
46	Asynchronous reset used instead of synchronous.	mohor	8097d 03h	/dbg_interface/tags/rel_15/rtl/
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8103d 22h	/dbg_interface/tags/rel_15/rtl/
44	Signal names changed to lower case.	mohor	8103d 22h	/dbg_interface/tags/rel_15/rtl/
43	Intentional error removed.	mohor	8108d 22h	/dbg_interface/tags/rel_15/rtl/