URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 90

Rev	Log message	Author	Age	Path
47	mon_cntl_o signals that controls monitor mux added.	mohor	8124d 18h	/dbg_interface/tags/rel_15/rtl/verilog/
46	Asynchronous reset used instead of synchronous.	mohor	8133d 00h	/dbg_interface/tags/rel_15/rtl/verilog/
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8139d 19h	/dbg_interface/tags/rel_15/rtl/verilog/
44	Signal names changed to lower case.	mohor	8139d 19h	/dbg_interface/tags/rel_15/rtl/verilog/
43	Intentional error removed.	mohor	8144d 19h	/dbg_interface/tags/rel_15/rtl/verilog/
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8144d 21h	/dbg_interface/tags/rel_15/rtl/verilog/
41	Function changed to logic because of some synthesis warnings.	mohor	8152d 18h	/dbg_interface/tags/rel_15/rtl/verilog/
40	Signal tdo_padoe_o changed back to tdo_padoen_o.	mohor	8166d 18h	/dbg_interface/tags/rel_15/rtl/verilog/
39	tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just not named correctly.	mohor	8167d 19h	/dbg_interface/tags/rel_15/rtl/verilog/
38	Few outputs for boundary scan chain added.	mohor	8180d 18h	/dbg_interface/tags/rel_15/rtl/verilog/