URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_16/] [bench/] - Rev 158

Rev	Log message	Author	Age	Path
88	temp3 version.	mohor	7461d 20h	/dbg_interface/tags/rel_16/bench/
87	tmp2 version.	mohor	7463d 01h	/dbg_interface/tags/rel_16/bench/
80	New version of the debug interface. Not finished, yet.	mohor	7475d 23h	/dbg_interface/tags/rel_16/bench/
75	Simulation files.	mohor	7536d 21h	/dbg_interface/tags/rel_16/bench/
73	CRC logic changed.	mohor	7536d 21h	/dbg_interface/tags/rel_16/bench/
63	Three more chains added for cpu debug access.	simons	7592d 23h	/dbg_interface/tags/rel_16/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8070d 22h	/dbg_interface/tags/rel_16/bench/
38	Few outputs for boundary scan chain added.	mohor	8126d 23h	/dbg_interface/tags/rel_16/bench/
36	Structure changed. Hooks for jtag chain added.	mohor	8130d 22h	/dbg_interface/tags/rel_16/bench/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8271d 01h	/dbg_interface/tags/rel_16/bench/