URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] - Rev 84

Rev	Log message	Author	Age	Path
53	Trst active high. Inverted on higher layer.	mohor	7979d 23h	/dbg_interface/tags/rel_19/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7979d 23h	/dbg_interface/tags/rel_19/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	8007d 11h	/dbg_interface/tags/rel_19/
50	Revision 1.5 of the document ready. WISHBONE Scan Chain changed.	mohor	8007d 12h	/dbg_interface/tags/rel_19/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8162d 23h	/dbg_interface/tags/rel_19/
46	Asynchronous reset used instead of synchronous.	mohor	8171d 05h	/dbg_interface/tags/rel_19/
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8178d 01h	/dbg_interface/tags/rel_19/
44	Signal names changed to lower case.	mohor	8178d 01h	/dbg_interface/tags/rel_19/
43	Intentional error removed.	mohor	8183d 00h	/dbg_interface/tags/rel_19/
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8183d 02h	/dbg_interface/tags/rel_19/