URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 114

Rev	Log message	Author	Age	Path
63	Three more chains added for cpu debug access.	simons	7616d 19h	/dbg_interface/tags/rel_19/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8094d 18h	/dbg_interface/tags/rel_19/bench/
38	Few outputs for boundary scan chain added.	mohor	8150d 18h	/dbg_interface/tags/rel_19/bench/
36	Structure changed. Hooks for jtag chain added.	mohor	8154d 17h	/dbg_interface/tags/rel_19/bench/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8294d 21h	/dbg_interface/tags/rel_19/bench/
15	bs_chain_o added.	mohor	8296d 22h	/dbg_interface/tags/rel_19/bench/
13	Signal names changed to lowercase.	mohor	8297d 23h	/dbg_interface/tags/rel_19/bench/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8298d 23h	/dbg_interface/tags/rel_19/bench/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8319d 19h	/dbg_interface/tags/rel_19/bench/
9	Working version. Few bugs fixed, comments added.	mohor	8323d 23h	/dbg_interface/tags/rel_19/bench/