URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] [verilog/] - Rev 158

Rev	Log message	Author	Age	Path
91	tmp version.	mohor	7490d 04h	/dbg_interface/tags/rel_19/bench/verilog/
90	tmp version.	mohor	7490d 23h	/dbg_interface/tags/rel_19/bench/verilog/
89	temp4 version.	mohor	7492d 05h	/dbg_interface/tags/rel_19/bench/verilog/
88	temp3 version.	mohor	7493d 00h	/dbg_interface/tags/rel_19/bench/verilog/
87	tmp2 version.	mohor	7494d 05h	/dbg_interface/tags/rel_19/bench/verilog/
80	New version of the debug interface. Not finished, yet.	mohor	7507d 03h	/dbg_interface/tags/rel_19/bench/verilog/
75	Simulation files.	mohor	7568d 01h	/dbg_interface/tags/rel_19/bench/verilog/
73	CRC logic changed.	mohor	7568d 01h	/dbg_interface/tags/rel_19/bench/verilog/
63	Three more chains added for cpu debug access.	simons	7624d 03h	/dbg_interface/tags/rel_19/bench/verilog/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8102d 02h	/dbg_interface/tags/rel_19/bench/verilog/