URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 101

Rev	Log message	Author	Age	Path
67	Lower two address lines must be always zero.	simons	7636d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
65	WB_CNTL register added, some syncronization fixes.	simons	7637d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
63	Three more chains added for cpu debug access.	simons	7657d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
61	Lapsus fixed.	simons	7685d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
59	Reset value for riscsel register set to 1.	simons	7685d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
57	Multiple cpu support added.	simons	7685d 10h	/dbg_interface/tags/rel_19/rtl/verilog/
53	Trst active high. Inverted on higher layer.	mohor	7952d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7952d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7979d 19h	/dbg_interface/tags/rel_19/rtl/verilog/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8135d 07h	/dbg_interface/tags/rel_19/rtl/verilog/