URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 108

Rev	Log message	Author	Age	Path
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7540d 06h	/dbg_interface/tags/rel_19/rtl/verilog/
77	MBIST chain connection fixed.	mohor	7601d 02h	/dbg_interface/tags/rel_19/rtl/verilog/
73	CRC logic changed.	mohor	7601d 04h	/dbg_interface/tags/rel_19/rtl/verilog/
71	Mbist support added.	simons	7603d 11h	/dbg_interface/tags/rel_19/rtl/verilog/
67	Lower two address lines must be always zero.	simons	7636d 07h	/dbg_interface/tags/rel_19/rtl/verilog/
65	WB_CNTL register added, some syncronization fixes.	simons	7637d 06h	/dbg_interface/tags/rel_19/rtl/verilog/
63	Three more chains added for cpu debug access.	simons	7657d 07h	/dbg_interface/tags/rel_19/rtl/verilog/
61	Lapsus fixed.	simons	7685d 07h	/dbg_interface/tags/rel_19/rtl/verilog/
59	Reset value for riscsel register set to 1.	simons	7685d 07h	/dbg_interface/tags/rel_19/rtl/verilog/
57	Multiple cpu support added.	simons	7685d 08h	/dbg_interface/tags/rel_19/rtl/verilog/