URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 63

Rev	Log message	Author	Age	Path
32	Stupid bug that was entered by previous update fixed.	mohor	8197d 03h	/dbg_interface/tags/rel_19/rtl/verilog/
31	trst synchronization is not needed and was removed.	mohor	8197d 04h	/dbg_interface/tags/rel_19/rtl/verilog/
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8208d 08h	/dbg_interface/tags/rel_19/rtl/verilog/
28	TDO and TDO Enable signal are separated into two signals.	mohor	8244d 05h	/dbg_interface/tags/rel_19/rtl/verilog/
27	Warnings from synthesys tools fixed.	mohor	8258d 06h	/dbg_interface/tags/rel_19/rtl/verilog/
26	Warnings from synthesys tools fixed.	mohor	8258d 06h	/dbg_interface/tags/rel_19/rtl/verilog/
25	trst signal is synchronized to wb_clk_i.	mohor	8259d 03h	/dbg_interface/tags/rel_19/rtl/verilog/
23	Trace disabled by default.	mohor	8266d 07h	/dbg_interface/tags/rel_19/rtl/verilog/
22	Register length fixed.	mohor	8266d 07h	/dbg_interface/tags/rel_19/rtl/verilog/
21	CRC is returned when chain selection data is transmitted.	mohor	8267d 03h	/dbg_interface/tags/rel_19/rtl/verilog/