URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] - Rev 96

Rev	Log message	Author	Age	Path
73	CRC logic changed.	mohor	7555d 07h	/dbg_interface/tags/rel_21/
71	Mbist support added.	simons	7557d 13h	/dbg_interface/tags/rel_21/
70	A pdf copy of existing doc document.	simons	7564d 15h	/dbg_interface/tags/rel_21/
69	WBCNTL added, multiple CPU support described.	simons	7585d 04h	/dbg_interface/tags/rel_21/
67	Lower two address lines must be always zero.	simons	7590d 09h	/dbg_interface/tags/rel_21/
65	WB_CNTL register added, some syncronization fixes.	simons	7591d 08h	/dbg_interface/tags/rel_21/
63	Three more chains added for cpu debug access.	simons	7611d 09h	/dbg_interface/tags/rel_21/
61	Lapsus fixed.	simons	7639d 09h	/dbg_interface/tags/rel_21/
59	Reset value for riscsel register set to 1.	simons	7639d 09h	/dbg_interface/tags/rel_21/
57	Multiple cpu support added.	simons	7639d 11h	/dbg_interface/tags/rel_21/