URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] - Rev 116

Rev	Log message	Author	Age	Path
75	Simulation files.	mohor	7552d 05h	/dbg_interface/tags/rel_21/bench/
73	CRC logic changed.	mohor	7552d 05h	/dbg_interface/tags/rel_21/bench/
63	Three more chains added for cpu debug access.	simons	7608d 08h	/dbg_interface/tags/rel_21/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8086d 07h	/dbg_interface/tags/rel_21/bench/
38	Few outputs for boundary scan chain added.	mohor	8142d 07h	/dbg_interface/tags/rel_21/bench/
36	Structure changed. Hooks for jtag chain added.	mohor	8146d 06h	/dbg_interface/tags/rel_21/bench/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8286d 10h	/dbg_interface/tags/rel_21/bench/
15	bs_chain_o added.	mohor	8288d 11h	/dbg_interface/tags/rel_21/bench/
13	Signal names changed to lowercase.	mohor	8289d 11h	/dbg_interface/tags/rel_21/bench/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8290d 12h	/dbg_interface/tags/rel_21/bench/