URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 116

Rev	Log message	Author	Age	Path
75	Simulation files.	mohor	7553d 23h	/dbg_interface/tags/rel_21/bench/verilog/
73	CRC logic changed.	mohor	7554d 00h	/dbg_interface/tags/rel_21/bench/verilog/
63	Three more chains added for cpu debug access.	simons	7610d 02h	/dbg_interface/tags/rel_21/bench/verilog/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8088d 01h	/dbg_interface/tags/rel_21/bench/verilog/
38	Few outputs for boundary scan chain added.	mohor	8144d 01h	/dbg_interface/tags/rel_21/bench/verilog/
36	Structure changed. Hooks for jtag chain added.	mohor	8148d 00h	/dbg_interface/tags/rel_21/bench/verilog/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8288d 04h	/dbg_interface/tags/rel_21/bench/verilog/
15	bs_chain_o added.	mohor	8290d 05h	/dbg_interface/tags/rel_21/bench/verilog/
13	Signal names changed to lowercase.	mohor	8291d 06h	/dbg_interface/tags/rel_21/bench/verilog/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8292d 06h	/dbg_interface/tags/rel_21/bench/verilog/