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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] - Rev 101

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Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7663d 20h /dbg_interface/tags/rel_21/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7664d 20h /dbg_interface/tags/rel_21/rtl/
63 Three more chains added for cpu debug access. simons 7684d 20h /dbg_interface/tags/rel_21/rtl/
61 Lapsus fixed. simons 7712d 20h /dbg_interface/tags/rel_21/rtl/
59 Reset value for riscsel register set to 1. simons 7712d 21h /dbg_interface/tags/rel_21/rtl/
57 Multiple cpu support added. simons 7712d 22h /dbg_interface/tags/rel_21/rtl/
53 Trst active high. Inverted on higher layer. mohor 7979d 20h /dbg_interface/tags/rel_21/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7979d 20h /dbg_interface/tags/rel_21/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8007d 08h /dbg_interface/tags/rel_21/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8162d 19h /dbg_interface/tags/rel_21/rtl/

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